The MOS transistor transconductance (gm) is a useful figure of merit in analogue circuit design. The ratio gm/Id (Id being the drain current of the transistor), sometimes referred to as its transconductance generation efficiency, is also sometimes of interest. FIG. 1 illustrates the tranconductance characteristics (gm) 150 as a function of a range of gate voltages Vg for a transistor. These are basic transistor characteristics for measuring the transconductance performance. The problem of these characteristics is that they provide very limited flexibility when applied for a given technology. The circuit designer must accept these characteristics as they are and needs to rely on circuit design techniques only to try to achieve the best circuit performance.
It is an aim of certain embodiments of the present disclosure to provide a transistor arrangement that has an improved transconductance characteristic for analogue design. In certain embodiments this results in a gm (quasi) plateau.
One of the circuit design techniques to influence the transconductance of a transistor is to vary the gate length and width of the transistor. It is noted that changing one aspect, the width, of a transistor has no impact on the ratio gm/Id. This is because both the transconductance and the drain current can scale with the width of the transistor. The second order figure of merit, i.e. the ratio gm/Id, can be relevant in applications such as amplifier design, in which the gain of the amplifier is related to the operating point of transistors of the amplifier. This figure of merit allows basic design decisions for power consumption, gain, bandwidth and transistor size to be made.
Altering the gate length of a transistor has a strong impact on the transconductance and the threshold voltage. For example, simply varying the gate length may result in one transistor having a significantly higher transconductance than other associated transistors in the circuit. As such, this can have an undesirable effect on the gm peaks of other associated transistors and therefore not result in a gm plateau.
Various transistor arrangements have been previously demonstrated in which the transconductance of the MOS transistors is varied to improve analogue performance. For example, it has been demonstrated to alter the transconductance characteristics of a transistor arrangement by varying the gate length to width ratios and differential biasing of each transistor of the transistor arrangement. The main objective of this arrangement is to reduce the third order intermodulation characteristics and therefore to make the transistors more linear. In a different arrangement, it has been demonstrated to bias differentially each gate of at least two gates of a transistor to achieve a constant transconductance performance. Improvement in transconductance performance is also achieved in a further arrangement in which field effect transistors are paired and biased using differential biasing to achieve the uniform transconductance. In these known arrangements, the transconductance has been modified from a device/circuit design perspective only. Furthermore, the DC biasing for each transistor has to be isolated from the other transistors, which requires using extra primitive devices to act as DC blocks. This adds complexity to the transistor arrangement and also adds to chip area. The reader is referred to U.S. Pat. No. 6,819,184, U.S. Pat. No. 7,629,627 and U.S. Pat. No. 5,777,518.